With multiple supply chain reports focusing on Intel’s EMIB-T chip packaging technology, analyst Ming-Chi Kuo has shared that TSMC’s next-generation packaging technology, CoPoS, will enter mass production in 2028. CoPoS, short for chip-on-panel-on-substrate, seeks to overcome the limitations of the current CoWoS (chip-on-wafer-on-substrate) packaging technology by increasing the area on which the GPU, memory and other chips are mounted in an AI chip. TSMC’s CoPoS Packaging Technology Will Use Glass Core Sandwiched Between ABF As A Substrate, Says Analyst With the demand for AI chips showing no signs of slowing down and Taiwan’s TSMC continuing to be the only supplier […]
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