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Intel Cracks The Encapsulation Wall Blocking Hyper-Large Chips, Pushing Advanced Packaging To 24x Reticle Size and Beyond

A close-up of a semiconductor wafer with visible circuitry patterns on a manufacturing machine.

Intel has overcome one big challenge that will lead to the creation of hyper-large chips beyond 12x reticle size through advanced packaging technologies. Intel Is Creating The World’s Most Advanced & Largest Chips in the US at Its New Mexico “Rio Rancho” Facility, Leveraging Next-Gen Packaging Innovations Modern-day chips don’t rely on a single piece of silicon, and instead utilize a range of silicon dies, interconnected together using the latest packaging solutions. The terminology used for such designs is chiplets, and chiplets were made to overcome scaling bottlenecks and the growing demand for compute. Inside Intel’s Rio Rancho, New Mexico […]

Read full article at https://wccftech.com/intel-cracks-encapsulation-wall-blocking-hyper-large-chips-using-advanced-packaging/