In a new research paper, AMD is exploring ways to stack L2 cache on its future chips, offering similar or better latency. 3D V-Cache But For L2: AMD Exploring Integrating Stacked L2 Caches Besides L3 For Future Chips AMD has published an interesting research paper titled “Balanced Latency Stacked Cache” with a patent application number of “US20260003794A1”. In this paper, AMD discloses techniques for a balanced latency stacked cache, where a stacked cache system includes a first cache die and at least a second cache die in a stacked orientation with the first cache die. We know that AMD already offers […]
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